1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which transmits data in serial to/from the exterior and reads/writes data in parallel from/to memory cells. In particular, the present invention relates to a technology of converting data at high speed.
2. Description of the Related Art
SDRAMs (Synchronous DRAMs) are known as a semiconductor integrated circuit operating their input/output interfaces at high speed in synchronization with a clock signal or the like to input/output data at high speed. Their transmitting data in serial to/from the exterior and reading/writing data in parallel from/to memory cells improve its data transmission speed.
FIG. 1 shows the outlines of an output interface unit in the SDRAM of this type.
An output interface unit 1 comprises a data selector 2, a parallel-serial converter 3, a shift register 4, and a data output buffer 5. This output interface unit 1 except the shift register 4 is formed for each of a plurality of data input/output terminals DQ.
The data selector 2 comprises four switches 2a consisting of CMOS transmission gates or the like. Each of the switches 2a receives data signals DB0-DB3 output from not-shown memory cells, and outputs one of the received signals as a data signal DBS0 (DBS1, DBS2, or DBS3) in accordance with address signals AD0 and AD1. In this diagram, the data selector 2 is shown connecting its switches when the address signals AD0 and AD1 are xe2x80x9c10xe2x80x9d in binary.
The parallel-serial converter 3 comprises four switches 3a each consisting of CMOS transmission gates or the like. The switches 3a are turned on upon the activation of connecting signals NA, NB, NC, and ND, and respectively transmit the data signals DBS0-DBS3 as a data output signal DOUT.
The shift register 4 performs shift operations in synchronization with a clock signal CLK, activating the connecting signals NA, NB, NC, and ND in this order.
The data output buffer 5 outputs serial read data transmitted as the data output signal DOUT to the data input/output terminal DQ.
In this SDRAM, the order of outputting the data signals DBS0-DBS3 in a read operation is determined in accordance with lower address signals AD0 and AD1 supplied from the exterior. Such an operating mode that data read from memory cells in parallel are successively output is generally referred to as a burst output mode.
FIG. 2 shows an example of the read operations by the SDRAM described above.
Initially, the SDRAM accepts a read command READ1 and address signals in synchronization with the CLK signal on the cycle 1 to start a read operation. In this example, the address signals AD0 and AD1 supplied along with the read command READ1 are xe2x80x9c10xe2x80x9d in binary.
The data selector 2 shown in FIG. 1 receives the address signals AD0 and AD1, and connects the switches 2a. The data signals DB0, DB1, DB2, and DB3 read from memory cells are transmitted as the data signals DBS2, DBS3, DBS0, and DBS1, respectively, through the data selector 2.
The shift register 4 activates the connecting signals NA, NB, NC, and ND in synchronization with the clock signal CLK on the cycles 3, 4, 5, and 6, respectively.
The switches 3a in the parallel-serial converter 3 receive the connecting signals NA, NB, NC, and ND, and sequentially output the data signals DBS2, DBS3, DBS0, and DBS1 as the data output signal DOUT.
Then, the data output signal DOUT of serial form is output to the data input/output terminal DQ via the data output buffer 5. That is, when the address signals AD0 and AD1 are xe2x80x9c10,xe2x80x9d the data signals are output in the order of DB2, DB3, DB0, and DB1 (4-bit burst output).
In synchronization with the clock signal CLK on the cycle 5, the SDRAM also accepts the next read command READ2 and address signals AD0 and AD1 (xe2x80x9c00xe2x80x9d in binary).
The data selector 2 switches over the individual switches 2a according to the address signals AD0 and AD1. Then, the data signals DB0, DB1, DB2, and DB3 read from memory cells are respectively transmitted as the data signals DBS0, DBS1, DBS2, and DBS3 through the date selector 2. In synchronization with the connecting signals NA, NB, NC, and ND sequentially activated, the parallel-serial converter 3 outputs the data signals DBS0, DBS1, DBS2, and DBS3 as the serial data output signal DOUT.
Then, the serial data output signal DOUT is output to the data input/output terminal DQ via the data output buffer 5. That is, when the address signals AD0 and AD1 are xe2x80x9c00,xe2x80x9d the data signals are output in the order of DB0, DB1, DB2, and DB3.
On the next read command READ3, the read data are output to the data input/output terminal DQ in the order of the data signals DB3, DB0, DB1, and DB2 in accordance with the address signals AD0 and AD1 (xe2x80x9c11xe2x80x9d in binary).
In the output interface unit 1 described above, the data signals DB0-DB3 are output to the exterior controlled by both the data selector 2 and the parallel-serial converter 3. Therefore, it is required to consider the timing margins of both the data selector 2 and the parallel-serial converter 3 in the timing design of the SDRAM.
In addition, the data signals DB0-DB3 are output to the exterior through the two switches 2a and 3a and this delays the outputs of the data signals by the propagation delay times of the switches 2a and 3a. 
As described above, in conventional SDRAMs, the output interface unit 1 has caused the data transmission speed of read data from memory cells to lower. SDRAMs are essentially characterized by operating their input/output interfaces at high speed. On this account, the output interface unit 1 needs to transmit read data from memory cells as fast as possible.
An object of the present invention is to transmit read data from memory cells at high speed.
Another object of the present invention is to perform a read operation at high speed in a semiconductor integrated circuit having memory cells.
Another object of the present invention is to perform a read operation at high speed in semiconductor integrated circuit having memory cells of a clock-synchronous type.
Another object of the present invention is to control the parallel-to-serial conversion of read data with a simple circuit.
Another object of the present invention is to perform a write operation at high speed in a semiconductor integrated circuit having memory cells.
According to one of the aspects of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches selected in a predetermined order. The switch control circuit controls the order of selecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order.
This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells.
According to another aspect of the semiconductor integrated circuit in the present invention, the serial data converted by the parallel-serial converter are output to the exterior through an output circuit. This can further heighten the speed of read operations, for example, in a semiconductor integrated circuit having a burst output function.
According to another aspect of the semiconductor integrated circuit in the present invention, each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior. This can heighten the speed of read operations, for example, in a clock-synchronous type of semiconductor integrated circuit having memory cells.
According to another aspect of the semiconductor integrated circuit in the present invention, the control signal is supplied from the exterior corresponding to a read operation in a memory cell. This makes it possible to change the bit order of serial data in real time in every read operation.
According to another aspect of the semiconductor integrated circuit in the present invention, the bit order of the serial data is changed by an address signal selecting a predetermined one of the memory cells. For example, a 1-bit address signal can be used to convert 2-bit parallel data into serial data in a predetermined bit order. A 2-bit address signal can be used to convert 4-bit parallel data into serial data in a predetermined bit order. In other words, the semiconductor integrated circuit having a burst output function can convert output data into serial data in a predetermined bit order without any delay in access time.
According to another aspect of the semiconductor integrated circuit in the present invention, the switch control circuit comprises a shift register having memory stages whose outputs are connected with the switches. The initial value of the shift register is set in accordance with the control signal. Shifting the shift register enables the switches to be connected in a predetermined order. This permits control over the bit order of the serial data with a simple circuit. The simplicity of the circuit also facilitates timing design and layout design.
According to another aspect of the semiconductor integrated circuit in the present invention, the address signal for selecting a predetermined one of the memory cells is supplied from the exterior. The initial value of the shift register is set in accordance with this address signal. Therefore, the semiconductor integrated circuit having a burst output function can convert output data into serial data in a predetermined bit order without any delay in access time.
According to another aspect of the semiconductor integrated circuit in the present invention, the shift register receives an inverting signal and inverts its shift direction in accordance with the inverting signal. Therefore, serial data in different bit orders can be generated by using the same shift register. For example, the inversion of a shift direction allows easy application of an interleave mode.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a serial-parallel converter for converting serial data to be written to memory cells into parallel data, and a switch control circuit for receiving a control signal and controlling the serial-parallel converter. The serial-parallel converter has a plurality of switches selected in a predetermined order. The switch control circuit controls the order of selecting the switches in accordance with the control signal so that serial data are converted into parallel data in a predetermined bit order.
This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for conversion circuits for changing the bit order of parallel data. This results in faster data write operations in memory cells.